Talk:Non-maskable interrupt
 | This article is rated Start-class on Wikipedia's content assessment scale. It is of interest to the following WikiProjects: | ||||||||||
| |||||||||||
Maskability of NMIs[edit]
>Some NMIs may be masked, but only by using proprietary methods specific to the particular NMI.
Actually, on AT and compatible chipsets NMI can be disabled if bit 7 of port 70h is high. This is well documented, and a source is here. NMI means the interrupt cannot be disabled by the CLI instruction or by the PIC, there are still other ways to disable it. System86 (talk) 00:13, 30 January 2008 (UTC)
- NMIs are ignored by x86 CPU in SMM mode without using any external PIC/chipset/controllers/etc. There's a way to unmask NMIs in SMM yet: http://www.rcollins.org/ddj/Mar97/Mar97.html#Tbl4 --xrgtn (talk) 12:35, 17 April 2012 (UTC)
Minimum timing between NMIs?[edit]
What happens if one NMI arrives while the previous is not completed? Or is this forbidden (and checked using some form of timing analysis)? Dpotop (talk) 14:32, 26 May 2008 (UTC)
ChazZeromus (talk) 01:47, 4 August 2009 (UTC) If your talking about x86 architecture, I do believe it simply task switches. Depending on the type of gate that the interrupt is associated with, a successful forced task switch will take place if operating in protected mode. It's somewhere in the Systems Programming manual from Intel.